There are many applications for volatile and non-volatile memory devices, such as digital cameras, measurement instruments and the like. A functional block diagram of a common memory device is shown in FIG. 1, purposely emphasizing only the output path of=data read from the memory. The data output path includes essentially a state machine OUTPUT—LPC controlling the stream of data as it is read from a standard memory core FLASH—CORE and placed on a first internal data bus DBUS<7:0> and an output buffer OUT—BUFFER, coupled to the state machine through a second internal bus BUSOUT<3:0>.
An internal timing signal CK—IN, generated by the internal buffer IN—BUFFER input with the external clock CK, synchronizes the execution of the operations of the state machine. The state machine receives data coming from the standard memory core FLASH—CORE through the internal data bus DBUS<7:0>, which may typically be an eight bit bus, and conveys them in serial mode with proper timing to the output buffer OUT—BUFFER. This buffer is enabled by an enabling signal OE generated by the state machine and includes an output stage FINAL—STAGE that produces the data on the output bus PAD—EXT<3:0>. Several largely used protocols require that the data read from the memory be made available on the output bus PAD—EXT<3:0> by a pre-established maximum time starting from the rising edge of the external clock. Because of delays of propagation of digital signals through the circuitry present along the output path of the memory device, it may be difficult to meet such a fundamental requirement. 
To more clearly illustrate the addressed technical problem, a well known type of memory device will be considered in conjunction with an equally well known type of protocol that specifically sets such a maximum time. In the ensuing description, reference will be made to an LPC (Low Pin Count) protocol, which is particularly important because of its popularity and widespread use, however all the considerations that will be made are valid, with the respective differences having been considered, even for other protocols setting the same requirement, such as the well known PCI and SPI protocols. For each cycle of the LPC protocol, only one byte is read in the way illustrated in FIG. 2. For the first twelve clock pulses, the external host of the memory device controls a system bus I/O (not shown in FIG. 1) connected to the output bus PAD—EXT<3:0>. During this first group of clock pulses the external host provides codes to the input circuits of the memory device for accessing the standard memory core thereof FLASH—CORE. 
The sequence of twelve clock pulses is so subdivided: one pulse for the START phase, one pulse for the CYCLE—TYPE phase that specifies whether the cycle of the LPC protocol is a READ or a WRITE cycle, eight clock pulses for the ADDRESS phase, in which the address of the memory sector in which the host must read or write data is provided, and two pulses for the TAR and TAR-Z phases signaling the handing over of the control on the system bus. After these last two clock cycles, the standard memory FLASH—CORE engages the system bus through the bus PAD—EXT<3:0>. 
Note that the memory device has received through an input interface all information necessary to carry out a READ command, through the sequence exemplified in FIG. 3. After the TAR phase, within the memory FLASH—CORE an “Address Transition Detection” (ATD) signal is produced and thus a reading, asynchronous with respect to the external clock CK, is started. The memory FLASH—CORE generates wait cycles, SYNC, during which it carries out internal operations. When the reading is completed, it outputs the read data and, by way of two further TAR cycles it transfers again the control of the system bus to the external host.
The state machine OUTPUT—LPC manages the transfer phase of the data read from the internal bus DBUS<7:0> to the output buffer OUT—BUFFER and, at the end of the process, it enables the output buffer to produce the read data on the output bus PAD—EXT<3:0>. The internal clock signal CK—IN is input to the state machine that controls the data stream OUTPUT—LPC and the state machine generates a logic enable signal OE of the output buffer after two periods of the internal clock signal CK—IN, as required by the specifications of the LPC protocol, thus loading the data present on the first internal bus DBUS<7:0> on the second internal bus BUSOUT<3:0>.
As stated before, the LPC specifications, as the specifications of similar protocols, establish a maximum output time starting from the rising edge of the external clock CK for producing the read data on the output bus. Such a maximum time delay TVAL must be respected each time the memory must load data on the first internal bus DBUS<7:0>. As depicted in FIG. 4, when two periods of the internal clock signal CK—IN have elapsed after that the data to be read had been made available on the internal data bus DBUS<7:0>, the state machine OUTPUT—LPC generates the enabling signal OE and produces the data to be read on the bus BUSOUT<3:0>. After a certain delay TOUT—BUF, introduced by the output buffer OUT—BUFFER, the data is finally produced on the output bus PAD—EXT<3:0>. 
Because of propagation delays through the circuits of the output path, the data to be read is made available on the bus PAD—EXT<3:0> after a time TVAL from the rising edge of the external clock CK. The time TVAL is the sum of three contributions: the delay TIO—BUF of the internal clock signal CK—IN with respect to the external clock signal CK; the load time TBUSOUT of data read from the memory on the second internal bus BUSOUT<3:0>; and the delay introduced by the output buffer TOUT—BUF; thusTVAL=TIO—BUF+TBUSOUT+TOUT—BUF   (1)
Without an accurate design of the circuits of the output path of the memory device, the time TVAL may easily exceed the maximum delay with respect to the rising edge of the external clock CK allowed by the particular protocol being used.